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single-chip 8-bit cmos microcomputer description the 7540 group is the 8-bit microcomputer based on the 740 family core technology. the 7540 group has a serial i/o, 8-bit timers, a 16-bit timer, and an a-d converter, and is useful for control of home electric appliances and office automation equipment. features ? basic machine-language instructions ....................................... 71 ? the minimum instruction execution time .......................... 0.50 s (at 8 mhz oscillation frequency for the shortest instruction) ? memory size rom ............................................ 16k to 32k bytes ram .............................................. 512 to 768 bytes ? programmable i/o ports ........................................................... 29 (25 in 32-pin version) ? interrupts .................................................. 15 sources, 15 vectors (14 sources, 14 vectors for 32-pin version) ? timers ............................................................................ 8-bit 5 4 16-bit 5 1 ? serial i/o1 ...................................................................... 8-bit 5 1 (uart or clock-synchronized) ? serial i/o2 ...................................................................... 8-bit 5 1 (clock-synchronized) ? a-d converter ................................................ 10-bit 5 8 channels (6 channels for 32-pin version) ? clock generating circuit ............................................. built-in type mitsubishi microcomputers 7540 group (low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting rc oscillation) ? watchdog timer ............................................................ 16-bit 5 1 ? power source voltage x in oscillation frequency at ceramic oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v at 4 mhz .................................................................... 2.4 to 5.5 v at 2 mhz .................................................................... 2.2 to 5.5 v x in oscillation frequency at rc oscillation at 4 mhz .................................................................... 4.0 to 5.5 v at 2 mhz .................................................................... 2.4 to 5.5 v at 1 mhz .................................................................... 2.2 to 5.5 v ? power dissipation ............................................ 25 mw (standard) ? operating temperature range ................................... C20 to 85 c (C40 to 85 c for extended operating temperature version) application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. note: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. pin configuration (top view) fig. 1 m37540m4-xxxgp, m37540e8gp pin configuration package type: 32p6b-a p0 7 p1 0 /r x d 1 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) p3 0 (led 0 ) v ss x out x in 9 10 11 12 13 14 15 16 2 8 7 6 5 3 1 4 v cc cnv ss reset p2 2 /an 2 p0 5 20 17 18 19 21 24 p0 2 /tz out p0 4 p0 3 /tx out p0 6 23 22 p0 1 /ty out p0 0 /cntr 1 p3 7 /int 0 m37540m4-xxxgp m37540e8gp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref preliminary notice: this is not a final specification. some parametric limits are subject to change.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 2 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 3 m37540m4-xxxsp, m37540e8sp pin configuration fig. 2 m37540m4-xxxfp, m37540e8fp pin configuration package type: 36p2r-a 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 0 /r x d 1 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 p0 7 p3 7 /int 0 reset m37540m4-xxxfp m37540e8fp p1 4 /cntr 0 p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 p0 7 p0 6 p0 5 p0 4 p3 0 (led 0 ) p2 5 /an 5 v ref reset p0 0 /cntr 1 p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) m37540m4-xxxsp m37540e8sp 32 p0 1 /ty out p0 2 /tz out p0 3 /tx out 14 15 16 p3 7 /int 0 p3 4 (led 4 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: 32p4b
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 3 preliminary notice: this is not a final specification. some parametric limits are subject to change. functional block fig. 4 functional block diagram (32p6b package) functional block diagram (package: 32p6b) x in out x si/o1(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a-d converter (10) v ref watchdog timer reset 0 14 int 0 16 17 si/o2(8) cntr 0 i/o port p0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) p0(8) 25 23 21 19 24 22 20 18 int 0 timer 1 (8) prescaler 1 (8) tx out
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 4 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 5 functional block diagram (36p2r package) functional block diagram (package: 36p2r) a-d converter (10) x in out x cpu v ss 18 reset 13 v cc 15 14 cnv ss p0(8) 34 32 30 28 33 31 29 27 p1(5) 31 35 2 36 7 5 6 4 p2(8) p3(8) 20 23 21 19 12 i/o port p2 i/o port p0 i/o port p1 i/o port p3 16 17 11 9 10 8 0 22 26 24 25 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out int 1
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 5 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 6 functional block diagram (32p4b package) functional block diagram (package: 32p4b) 16 11 13 12 p1(5) 31 31 2 32 5 4 p2(6) p3(6) 17 20 18 10 14 15 9 7 8 6 0 19 21 22 p0(8) 30 28 26 24 29 27 25 23 a-d converter (10) x in out x cpu v ss reset v cc cnv ss i/o port p2 i/o port p0 i/o port p1 i/o port p3 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 6 preliminary notice: this is not a final specification. some parametric limits are subject to change. pin description table 1 pin description function ?apply voltage of 2.2C5.5 v to vcc, and 0 v to vss. ?reference voltage input pin for a-d converter ?chip operating mode control pin, which is always connected to vss. ?reset input pin for active l ?input and output pins for main clock generating circuit ?connect a ceramic resonator or quartz crystal oscillator between the x in and x out pins. ?for using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. ?if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. function expect a port function name power source analog reference voltage cnvss reset input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 pin vcc, vss v ref cnvss reset x in p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 Cp0 7 p1 0 /rxd 1 p1 1 /txd 1 ?8-bit i/o port. ?i/o direction register allows each pin to be individually pro- grammed as either input or output. ?cmos compatible input level ?cmos 3-state output structure ?whether a built-in pull-up resistor is to be used or not can be determined by program. ?5-bit i/o port ?i/o direction register allows each pin to be individually pro- grammed as either input or output. ?cmos compatible input level ?cmos 3-state output structure ?cmos/ttl level can be switched for p1 0, p1 2 and p1 3 ?8-bit i/o port having almost the same function as p0 ?cmos compatible input level ?cmos 3-state output structure ?8-bit i/o port ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level (cmos/ttl level can be switched for p3 6 and p3 7 ). ?cmos 3-state output structure ?p3 0 to p3 6 can output a large current for driving led. ? key-input (key-on wake up interrupt input) pins ? timer y, timer z, timer x and timer a function pin ?serial i/o1 function pin ?serial i/o1 function pin ?serial i/o2 function pin ?whether a built-in pull-up resistor is to be used or not can be determined by program. x out ?timer x function pin ?input pins for a-d converter ?interrupt input pins p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 C p2 7 /an 7 p3 0 Cp3 5 p3 6 /int 1 p3 7 /int 0
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 7 preliminary notice: this is not a final specification. some parametric limits are subject to change. group expansion mitsubishi plans to expand the 7540 group as follow: memory type support for mask rom version, one time prom version, and emu- lator mcu . memory size rom/prom size ................................................ 16 k to 32 k bytes ram size ................................................................ 512 to 768 bytes package 32p4b ........................................... 32-pin shrink plastic molded dip 32p6b-a ...................................... 0.8 mm-pitch plastic molded qfp 36p2r-a ..................................... 0.8 mm-pitch plastic molded sop 42s1m ..................................... 42-pin shrink ceramic piggy back fig. 7 memory expansion plan currently supported products are listed below. table 2 list of supported products product m37540m4-xxxsp m37540m4-xxxfp M37540M4T-XXXFP m37540m4-xxxgp m37540m4t-xxxgp m37540e8sp m37540e8fp m37540e8gp m37540rss (p) rom size (bytes) rom size for user () 16384 (16254) ram size (bytes) package 32p4b 36p2r-a 32p6b-a remarks mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version mask rom version (extended operating temperature version) one time prom version (blank) one time prom version (blank) one time prom version (blank) emulator mcu 512 32768 (32638) 768 768 32p4b 36p2r-a 32p6b-a 42s1m 384 32k rom size (bytes) ram size (bytes) 512 768 16k 0 under development m37540e8 m37540m4 m37540m4t under development under development note: products under development?he development schedule and specification may be revised without notice.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 8 preliminary notice: this is not a final specification. some parametric limits are subject to change. functional description central processing unit (cpu) the 7540 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the 740 family software manual for details on each instruction set. machine-resident 740 family instructions are as follows: 1. the fst and slw instructions cannot be used. 2. the mul and div instructions can be used. 3. the wit instruction can be used. 4. the stp instruction can be used. (this instruction cannot be used while cpu operates by a ring oscil- lator.) [cpu mode register] cpum the cpu mode register contains the stack page selection bit. this register is allocated at address 003b 16 . switching method of cpu mode register switch the cpu mode register (cpum) at the head of program after releasing reset in the following method. fig. 9 switching method of cpu mode register fig. 8 structure of cpu mode register oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( f ) = f(x in )/2 (high-speed mode) 0 1 : f( f ) = f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f( f ) = f(x in ) (double-speed mode)(note 2) ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu ?37540rss?) do not use these when an rc oscillation is selected. after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with a built-in ring oscillator an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. switch to other mode except a ring oscillator. at the same time, select the double-speed, high-speed, or middle-speed mode. wait by ring oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement).
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 9 preliminary notice: this is not a final specification. some parametric limits are subject to change. memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 10 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 512 768 xxxx 16 023f 16 033f 16 16384 32768 c000 16 8000 16 c080 16 8080 16 yyyy 16 zzzz 16 ram rom reserved area sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved rom area address zzzz 16
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 10 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 11 memory map of special function register (sfr) note : do not access to the sfr area including nothing. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a-d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) one-shot start register (ons) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) serial i/o2 register (sio2) a-d control register (adcon) a-d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) timer y, z mode register (tyzm) prescaler y (prey) timer y secondary (tys) timer y primary (typ) timer y, z waveform output control register (pum) prescaler z (prez) timer z secondary (tzs) timer z primary (tzp) interrupt request register 2 (ireq2) interrupt control register 2 (icon2)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 11 preliminary notice: this is not a final specification. some parametric limits are subject to change. i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/out- put direction of each pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. when 1 is set to the bit corresponding to a pin, this pin becomes an output port. when 0 is set to the bit, the pin becomes an input port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are floating, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2, p1 3, p3 6, and p3 7 by program. fig. 13 structure of port p1p3 control register fig. 12 structure of pull-up control register pull-up control register (pull: address 0016 16 , initial value: 00 16 ) p0 0 pull-up control bit p0 1 pull-up control bit p0 2 , p0 3 pull-up control bit p0 4 ?p0 7 pull-up control bit p3 0 ?p3 3 pull-up control bit p3 4 pull-up control bit p3 5 , p3 6 pull-up control bit p3 7 pull-up control bit b7 b0 0 : pull-up off 1 : pull-up on note 1: pins set to output ports are disconnected from pull-up control. 2: set the p3 5 , p3 6 pull-up control bit to ??(initial value: ?? for 32-pin version. port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 p3 7 /int 0 input level selection bit 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit 0 : cmos level 1 : ttl level p1 0 ,p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level not used note: keep setting the p3 6 /int 1 input level selection bit to ??(initial value) for 32-pin version.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 12 preliminary notice: this is not a final specification. some parametric limits are subject to change. table 3 i/o port function table name i/o port p0 i/o port p1 i/o port p2 i/o port p3 pin p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 Cp0 7 p1 0 /rxd 1 p1 1 /txd 1 input/output i/o individual bits i/o format ?cmos compatible input level ?cmos 3-state output (note) non-port function key input interrupt related sfrs diagram no. (1) (2) (3) (4) note: ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 are cmos/ttl level. pull-up control register timer y mode register timer z mode register timer x mode register timer y,z waveform out- put control register timer a mode register serial i/o1 control register serial i/o1 function input/output serial i/o2 function input/output timer x function input/output a-d conversion input external interrupt input serial i/o1 control register serial i/o2 control register timer x mode register a-d control register interrupt edge selection register (5) (6) (7) (8) (9) (10) (11) (12) p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 Cp2 7 /an 7 p3 0 Cp3 5 p3 6 /int 1 p3 7 /int 0
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 13 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 14 block diagram of ports (1) (6)port p1 1 data bus port latch serial i/o1 output p1 1 /t x d 1 p-channel output disable bit (5)port p1 0 (4)ports p0 4 p0 7 (1)port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit cntr 1 interrupt input (2)ports p0 1, p0 2 pulse output mode timer output (7)port p1 2 serial i/o1, serial i/o2 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit s clk2 pin selection bit (3)port p0 3 direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch pull-up control to key input interrupt generating circuit timer output p0 3 /tx out output valid direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch serial i/o1 enable bit receive enable bit serial i/o1 input p1 0 , p1 2 , p1 3 input level selection bit direction register serial i/o1 enable bit transmit enable bit direction register data bus port latch serial i/o1, serial i/o2 clock input p1 0 , p1 2 , p1 3 input level selection bit * * * p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 14 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 15 block diagram of ports (2) pull-up control int interrupt input p3 input level selection bit (11) ports p3 0 ?3 5 pull-up control (9) port p1 4 data bus serial i/o1 ready output serial i/o2 output serial i/o2 input s data2 pin selection bit port latch direction register s data2 output in operation signal cntr 0 interrupt input pulse output mode timer output p1 0 , p1 2 , p1 3 input level selection bit serial i/o mode selection bit serial i/o1 enable bit s rdy1 output enable bit p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. data bus port latch direction register data bus port latch direction register data bus port latch direction register a-d converter input analog input pin selection bit (12) ports p3 6 , p3 7 data bus port latch direction register * * (10) ports p2 0 ?2 7 * (8) port p1 3
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 15 preliminary notice: this is not a final specification. some parametric limits are subject to change. interrupts interrupts occur by 15 different sources : 5 external sources, 9 inter- nal sources and 1 software source. interrupt control all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. when the interrupt enable bit and the interrupt request bit are set to 1 and the interrupt disable flag is set to 0, an interrupt is accepted. the interrupt request bit can be cleared by program but not be set. the interrupt enable bit can be set and cleared by program. the reset and brk instruction interrupt can never be disabled with any flag or bit. all interrupts except these are disabled when the in- terrupt disable flag is set. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status regis- ter are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. notes on use when the active edge of an external interrupt (int 0 , int 1 ,cntr 0 ) is set, the interrupt request bit may be set. therefore, please take following sequence: 1. disable the external interrupt which is selected. 2. change the active edge in interrupt edge selection register. (in case of cntr 0 : timer x mode register, in case of cntr 1 : timer a mode register) 3. clear the set interrupt request bit to 0. 4. enable the external interrupt which is selected. table 4 interrupt vector address and priority vector addresses (note 1) high-order priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 low-order interrupt request generating conditions at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer x underflow at timer y underflow at timer z underflow at timer a underflow at completion of transmit/receive shift at completion of a-d conversion at timer 1 underflow not available at brk instruction execution remarks non-maskable valid only when serial i/o1 is selected valid only when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow non-maskable software interrupt interrupt source reset (note 2) serial i/o1 receive serial i/o1 transmit int 0 int 1 (note 3) key-on wake-up cntr 0 cntr 1 timer x timer y timer z timer a serial i/o2 a-d conversion timer 1 reserved area brk instruction fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: it is an interrupt which can use only for 36 pin version.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 16 interrupt control fig. 17 structure of interrupt-related registers interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active not used (returns ??when read) p0 0 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled (intedge : address 003a 16 ) interrupt request register 1 serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit int 0 interrupt request bit int 1 interrupt request bit key-on wake up interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) b7 b0 interrupt control register 1 serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit key-on wake up interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer x interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled (icon1 : address 003e 16 ) interrupt request register 2 timer y interrupt request bit timer z interrupt request bit timer a interrupt request bit serial i/o2 interrupt request bit a-d conversion interrupt request bit timer 1 interrupt request bit not used (returns ??when read) 0 : no interrupt request issued 1 : interrupt request issued (ireq2 : address 003d 16 ) b7 b0 interrupt control register 2 timer y interrupt enable bit timer z interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit a-d conversion interrupt enable bit timer 1 interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 )
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 17 preliminary notice: this is not a final specification. some parametric limits are subject to change. key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying l level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from 1 to 0. an example of using a key input interrupt is shown in fig- ure 18, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 18 connection example when using key input interrupt and port p0 block diagram port pxx ??level output pull register bit 3 = ?? port p0 7 latch port p0 7 direction register = ? ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos output buffer pull register bit 3 = ?? port p0 6 latch port p0 6 direction register = ? ** * p0 6 output pull register bit 3 = ?? port p0 5 latch port p0 5 direction register = ? ** * p0 5 output pull register bit 3 = ?? port p0 4 latch port p0 4 direction register = ? ** * p0 4 output pull register bit 2 = ?? port p0 3 latch port p0 3 direction register = ? ** * p0 3 input pull register bit 2 = ?? port p0 2 latch port p0 2 direction register = ? ** * p0 2 input pull register bit 1 = ?? port p0 1 latch port p0 1 direction register = ? ** * p0 1 input pull register bit 0 = ?? port p0 0 latch port p0 0 direction register = ? ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 18 preliminary notice: this is not a final specification. some parametric limits are subject to change. timers the 7540 group has 5 timers: timer 1, timer a, timer x, timer y and timer z. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches 0, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the inter- rupt request bit corresponding to each timer is set to 1. l timer 1 prescaler 1 always counts f(x in )/16. timer 1 always counts the prescaler 1 output and periodically sets the interrupt request bit. l timer a timer a is a 16-bit timer that can be selected in one of four modes. ? timer mode the timer counts f(x in )/16. ? period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer a latch is reloaded in timer a and timer a continues counting down. ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer a is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. ? event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. ? pulse width hl continuously measure-ment mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. n note l cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 19 structure of timer a mode register timer a mode register (tam : address 001d 16 ) b7 b0 not used (return ??when read) timer a operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer a stop control bit 0 : count start 1 : count stop
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 19 preliminary notice: this is not a final specification. some parametric limits are subject to change. l timer x timer x can be selected in one of 4 operating modes by setting the timer x mode register. ? timer mode the timer counts the signal selected by the timer x count source selection bits. ? pulse output mode the timer counts the signal selected by the timer x count source selection bits, and outputs a signal whose polarity is inverted each time the timer value reaches 0, from the cntr 0 pin. when the cntr 0 active edge switch bit is 0, the output of the cntr 0 pin is started with an h output. at 1, this output is started with an l output. when using a timer in this mode, set the port p1 4 direction register to output mode. also, in the pulse output mode, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting the p0 3 /tx out output valid bit to 1 . when using a timer in this mode, set the port p0 3 direc- tion register to output mode. ? event counter mode the operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the cntr 0 pin. when the cntr 0 active edge switch bit is 0, the timer counts the rising edge of the cntr 0 pin. when this bit is 1, the timer counts the falling edge of the cntr 0 pin. ? pulse width measurement mode when the cntr 0 active edge switch bit is 0, the timer counts the signal selected by the timer x count source selection bit while the cntr 0 pin is h. when this bit is 1, the timer counts the signal while the cntr 0 pin is l. in any mode, the timer count can be stopped by setting the timer x count stop bit to 1. each time the timer overflows, the interrupt request bit is set. fig. 20 structure of timer x mode register fig. 21 timer count source set register timer x mode register (txm : address 002b 16 ) cntr 0 active edge switch bit 0 : interrupt at falling edge count at rising edge (in event counter mode) 1 : interrupt at rising edge count at falling edge (in event counter mode) timer x operating mode bits b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode not used (return ??when read) timer x count stop bit 0 : count start 1 : count stop b7 b0 p0 3 /tx out output valid bit 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) timer count source set register (tcss : address 002e 16 ) b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) 1 1 : not available timer y count source selection bits b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output (note) 1 1 : not available timer z count source selection bits b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available fix this bit to ?? not used (return ??when read) note : system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 20 preliminary notice: this is not a final specification. some parametric limits are subject to change. l timer y timer y is an 8-bit timer and can be selected in one of 2 operating modes by setting the timer y, z mode register (tyzm). ? timer mode ? programmable waveform generation mode the division ratio of timer y and prescaler y is 1/(n+1) provided that the value of the timer latch or prescaler y latch is n. (1)timer mode ? mode select timer mode is selected by setting timer y operation mode bit (b0) of tyzm to 0. ? count source select the count source is f(x in )/2 or f(x in )/16. ? interrupt when an underflow occurs, timer y interrupt request bit (b0) of ireq2 is set to 1. ? operation description after reset release, timer y is operating because the timer y count stop bit (b3) of tyzm is 0. timer operation is stopped by setting b3 of tyzm to 1. in the timer mode, the timer count value is set by timer y primary latch (typ). when a value is set to typ while timer is stopped, the setting value is written to latch and timer si- multaneously. when timer y reaches 00, an underflow occurs at the next count pulse, and the timer y latch is reloaded into the timer and count continues. when timer value is changed during the count opera- tion, either writing to latch and timer simultaneously or writing to only latch can be selected by setting the timer y write control bit (b2) of tyzm. when selecting writing to only latch, the timer count value is changed after the next underflow. (2)programmable waveform generation mode ? mode select timer mode is selected by setting timer y operation mode bit (b0) of tyzm to 1. when this mode is selected, set timer y write control bit (b2) of tyzm to 1 (writing to only latch selected). ? count source select the count source is f(x in )/2 or f(x in )/16. ? interrupt when an underflow occurs, timer y interrupt request bit (b0) of ireq is set to 1. ? operation description after reset release, timer y is operating because the timer y count stop bit (b3) of tyzm is 0. mcu operates in the programmable waveform generation mode when timer y operation mode bit (b0) of tyzm is set to 1 and b3 to 0 after timer y operation is stopped by setting b3 of tyzm to 1. in the programmable waveform generation mode, timer counts the setting value of timer y primary latch (typ) and the setting value of timer y secondary latch (tys) alternately, the waveform inverted each time typ and tys underflow is output from ty out pin. the active edge of output waveform is set by the timer y output level latch (b4) of the timer y, z waveform output control register (pum). when 0 is set to b4 of pum, the initial state of timer at stop is l, and h interval by the setting value of typ or l interval by the setting value of tys is output alternately. when 1 is set to b4 of pum, the initial state of timer at stop is h, and l interval by the setting value of typ or h interval by the setting value of tys is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer y primary wave- form extension control bit (b0) and the timer y secondary wave- form extension control bit (b1) of pum to 1. as a result, the wave- forms of more accurate resolution can be output. when b0 and b1 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: ftyout = (2 5 tmcl)/(2 5 (typ+1) + 2 5 (tys) + (expyp + expys)) duty: dtyout = (2 5 (typ + 1)) + expyp)/(2 5 (tys + 1) + expys)) tmcl: timer y count clock f(x in )/2 or f(x in )/16 typ: timer y primary latch (8 bits) tys: timer y secondary latch (8 bits) expyp: timer y primary waveform extension control bit (1 bit) expys: timer y secondary waveform extension control bit (1 bit) when using the programmable waveform generation mode, note the following; notes on using the programmable waveform generation mode ? when setting and changing typ, tys, expyp and expys, write to typ at last because the setting to them is executed all at once by writing to typ. even when typ is not changed, write the same value. the value is reloaded to timer at the beginning of the next primary interval. ? set by software in order not to execute the writing to timer y pri- mary and the timing of timer underflow simultaneously. when read- ing the timer y secondary, the undefined value is read out. how- ever, while timer counts the setting value of the timer y secondary, the count values at the secondary interval can be identified by reading the timer y primary. ? in this mode, set port p0 1 which is also used as ty out pin to output. ? b0 and b1 of pum can be used only when 00 16 is set to prescaler y.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 21 preliminary notice: this is not a final specification. some parametric limits are subject to change. l timer z timer z is an 8-bit timer and can be selected in one of 4 operating modes by setting the timer yz mode register (tyzm). ? timer mode ? programmable waveform generation mode ? programmable one-shot generation mode ? programmable wait one-shot generation mode the division ratio of timer z and prescaler z is 1/(n+1) provided that the value of the timer z latch or prescaler z latch is n. (1)timer mode ? mode select timer mode is selected by setting timer z operation mode bits (b5,b4) of tyzm to 00. ? count source select the count source is f(x in )/2, f(x in )/16 or timer y underflow. ? interrupt when an underflow occurs, timer z interrupt request bit (b1) of ireq2 is set to 1. ? operation description after reset release, timer z is operating because the timer z count stop bit (b7) is 0. timer operation is stopped by setting b7 of tyzm to 1. in the timer mode, the timer count value is set by timer z primary latch (tzp). when a value is set to tzp while timer is stopped, the setting value is written to latch and timer simulta- neously. when timer z reaches 00, an underflow occurs at the next count pulse, and the timer z latch is reloaded into the timer and count continues. when timer value is changed during the count opera- tion, either writing to latch and timer simultaneously or writing to only latch can be selected by setting the timer z write control bit (b6) of tyzm. when selecting writing to only latch, the timer count value is changed after the next underflow. (2)programmable waveform generation mode ? mode select timer mode is selected by setting timer z operation mode bits (b5,b4) of tyzm to 01. when this mode is selected, set timer z write control bit (b6) of tyzm to 1 (writing to only latch selected). ? count source select the count source is f(x in )/2, f(x in )/16 or timer y underflow. ? interrupt when an underflow occurs, timer z interrupt request bit (b1) of ireq is set to 1. ? operation description after reset release, timer z is operating because the timer z count stop bit (b7) of tyzm is 0. mcu operates in the programmable waveform generation mode when timer z operation mode bits (b5, b4) of tyzm is set to 01 and b7 to 0 after timer z operation is stopped by setting b7 of tyzm to 1. in the programmable waveform generation mode, timer counts the setting value of timer z primary latch (tzp) and the setting value of timer z secondary latch (tzs) alternately, the waveform inverted each time tzp and tzs underflow is output from tz out pin. the active edge of output waveform is set by the timer z output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, the initial state of timer at stop is l, and h interval by the setting value of tzp or l interval by the setting value of tzs is output alternately. when 1 is set to b5 of pum, the initial state of timer at stop is h, and l interval by the setting value of tzp or h interval by the setting value of tzs is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer z primary wave- form extension control bit (b2) and the timer z secondary wave- form extension control bit (b3) of pum to 1. as a result, the wave- forms of more accurate resolution can be output. when b2 and b3 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: ftzout = (2 5 tmcl)/(2 5 (tzp + 1)+2 5 (tzs) + (expzp + expzs)) duty: dtzout = (2 5 (tzp + 1)) + expzp)/(2 5 (tzs+1) + expzs)) tmcl: timer z count clock f(x in )/2 or f(x in )/16 tzp: timer z primary latch (8 bits) tzs: timer z secondary latch (8 bits) expzp: timer z primary waveform extension control bit (1 bit) expzs: timer z secondary waveform extension control bit (1 bit) when using the programmable waveform generation mode, note the following; notes on using the programmable waveform generation mode ? when setting and changing tzp, tzs, expzp and expzs, write to tzp at last because the setting to them is executed all at once by writing to tzp. even when tzp is not changed, write the same value. the value is reloaded to timer at the beginning of the next primary interval. ? set by software in order not to execute the writing to timer z pri- mary and the timing of timer underflow simultaneously. when read- ing the timer z secondary, the undefined value is read out. how- ever, while timer counts the setting value of the timer z secondary, the count values at the secondary interval can be identified by reading the timer z primary. ? in this mode, set port p0 2 which is also used as tz out pin to out- put. ? b2 and b3 of pum can be used only when 00 16 is set to prescaler z and f(x in )/2 or f(x in )/16 is selected as the timer z count source.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 22 preliminary notice: this is not a final specification. some parametric limits are subject to change. (3)programmable one-shot generation mode ? mode select timer mode is selected by setting timer z operation mode bits (b5,b4) of tyzm to 10. when this mode is selected, set timer z write control bit (b6) of tyzm to 1 (writing to only latch selected). ? count source select the count source is f(x in )/2, f(x in )/16 or timer y underflow. ? interrupt when an underflow occurs, timer z interrupt request bit (b1) of ireq2 is set to 1. ? operation description after reset release, timer z is operating because the timer z count stop bit (b7) of tyzm is 0. mcu operates in the programmable one-shot generation mode when timer z operation mode bits (b5, b4) of tyzm is set to 10 after timer z operation is stopped by setting b7 of tyzm to 1. timer z is enabled to accept the one-shot start trigger when 0 is written to b7 of tyzm after the timer count value is set to the timer z primary latch (tzp). in this state, when 1 is written to the timer z one-shot start bit (b0) of the one-shot start register (ons), timer z starts count operation, at the same time, the output of tz out pin is inverted. timer z counts down the value of tzp and stops after the output of tz out pin is inverted to the same level as the initial state when an underflow occurs. in this time, the next one-shot pulse can be output by writing b0 of ons to 1 because this bit is initialized to 0. the active edge of the output waveform from tz out pin is set by the timer z output level latch (b5) of pum. when 0 is set to b5 of pum, the initial level of timer at stop is l and h is output at the same time when timer starts. h is output in the count interval of tzp, and the output is inverted to l and stopped when an under- flow occurs. also, when 1 is set to b5 of pum, the initial level of timer at stop is h and l is output at the same time when timer starts. l is output in the count interval of tzp, and the output is inverted to h and stopped when an underflow occurs. when the int0 pin one-shot trigger control bit (b6) of pum is set to 1, the one-shot pulse can be output by using the input of int0 pin as a trigger. the active edge of the pulse input to int0 pin as the trigger can be selected by the int0 pin one-shot trigger active edge selection bit (b7) of pum. the trigger is accepted and the one-shot pulse is generated by the falling edge of int0 pin input when 0 is set to b7 of pum or the rising edge of int0 pin input when 1 is set to the b7 of pum. also, the int0 interrupt occurs when the trigger is input from the int0 pin by setting the int0 interrupt edge selection bit (b0) of the interrupt edge selection register (intedge) and the int0 inter- rupt enable bit (b2) of the interrupt control register 1 (icon1). even when the trigger by the int0 pin input is selected, the one-shot pulse can be output by writing to b0 of ons. also, in this mode, the waveform output interval of the one-shot pulse can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (b2) to 1. as a result, the waveforms of more accurate resolution can be output. when using the programmable one-shot generation mode, note the following; notes on using the programmable one-shot generation mode ? when setting and changing tzp and expzs, write to tzp at last because the setting to them is executed all at once by writing to tzp. even when tzp is not changed, write the same value. the value is reloaded to timer at the beginning of the next primary in- terval. ? set by software in order not to execute the writing to timer z pri- mary and the timing of timer underflow simultaneously. when read- ing the timer z secondary, the undefined value is read out. how- ever, while timer counts the setting value of the timer z secondary, the count values at the secondary interval can be identified by reading the timer z primary. ? in this mode, set port p0 2 which is also used as tz out pin to output. ? b2 of pum can be used only when 00 16 is set to prescaler z and f(x in )/2 or f(x in )/16 is selected as the timer z count source.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 23 preliminary notice: this is not a final specification. some parametric limits are subject to change. (4)programmable wait one-shot generation mode ? mode select timer mode is selected by setting timer z operation mode bits (b5,b4) of tyzm to 11. when this mode is selected, set timer z write control bit (b6) of tyzm to 1 (writing to only latch selected). ? count source select the count source is f(x in )/2, f(x in )/16 or timer y underflow. ? interrupt when an underflow occurs, timer z interrupt request bit (b1) of ireq is set to 1. ? operation description after reset release, timer z is operating because the timer z count stop bit (b7) of tyzm is 0. mcu operates in the programmable wait one-shot generation mode when timer z operation mode bits (b5, b4) of tyzm is set to 11 after timer z operation is stopped by setting b7 of tyzm to 1. timer z is enabled to accept the one-shot start trigger when 0 is written to b7 of tyzm after the timer count values are set to the timer z primary latch (tzp) and the timer z secondary latch (tzs). in this state, when 1 is written to the timer z one-shot start bit (b0) of ons, timer z starts count operation. unlike the program- mable one-shot generation mode, the output of tz out pin is not changed until the timer counts tzp and an underflow occurs. when the timer z counts tzp and an underflow occurs, tzs is reloaded to timer, at the same time, the output of the tz out pin is inverted. timer z counts down the value of tzp and stops after the output of tz out pin is inverted to the same level as the initial state when an underflow occurs. in this time, the next one-shot pulse can be output by writing b0 of ons to 1 because this bit is initialized to 0. the active edge of the output waveform from tz out pin is set by the timer z output level latch (b5) of pum. when 0 is set to b5 of pum, the initial level of timer at stop and the tzp count interval are l and inverted to h at the same time when an underflow occurs. h is output in the count interval of tzs, and the output is inverted to l and stopped when an underflow occurs. also, when 1 is set to b5 of pum, the initial level of timer at stop and the tzp count interval are h and inverted to l at the same time when an underflow occurs. l is output in the count interval of tzs, and the output is inverted to h and stopped when an underflow occurs. when the int0 pin one-shot trigger control bit (b6) of pum is set to 1, the one-shot pulse can be output by using the input of int0 pin as a trigger. the active edge of the pulse input to int0 pin as the trigger can be selected by the int0 pin one-shot trigger active edge selection bit (b7) of pum. the trigger is accepted and the one-shot pulse is generated by the falling edge of int0 pin input when 0 is set to b7 of pum or the rising edge of int0 pin input when 1 is set to the b7 of pum. also, the int0 interrupt occurs when the trigger is input from the int0 pin by setting the int0 interrupt edge selection bit (b0) of the interrupt edge selection register (intedge) and the int0 inter- rupt enable bit (b2) of the interrupt control register 1 (icon1). even when the trigger by the int0 pin input is selected, the one-shot pulse can be output by writing to b0 of ons. also, in this mode, the waveform output interval of the one-shot pulse can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (b2) to 1. as a result, the waveforms of more accurate resolution can be output. when using the programmable wait one-shot generation mode, note the following; notes on using the programmable wait one-shot generation mode ? when setting and changing tzp, tzs, expzp and expzs, write to tzp at last because the setting to them is executed all at once by writing to tzp. even when tzp is not changed, write the same value. the value is reloaded to timer at the beginning of the next primary interval. ? set by software in order not to execute the writing to timer z pri- mary and the timing of timer underflow simultaneously. when read- ing the timer z secondary, the undefined value is read out. how- ever, while timer counts the setting value of the timer z secondary, the count values at the secondary interval can be identified by reading the timer z primary. ? in this mode, set port p0 2 which is also used as tz out pin to output. ? b2 of pum can be used only when 00 16 is set to prescaler z and f(x in )/2 or f(x in )/16 is selected as the timer z count source.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 24 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 23 structure of timer yz waveform output control register fig. 24 structure of one-shot start register fig. 22 structure of timer y, z mode register b7 b0 timer y, z mode register (tyzm : address 0020 16 ) timer y operation mode bit 0 : timer mode 1 : programmable waveform generation mode not used (return ??when read) timer y write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer y count stop bit 0 : count start 1 : count stop timer z count source selection bits b5 b4 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode timer z write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer z count stop bit 0 : count start 1 : count stop b7 b0 timer y, z waveform output control register (pum : address 0024 16 ) timer y primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y output level latch 0 : ??output 1 : ??output timer z output level latch 0 : ??output 1 : ??output int0 pin one-shot trigger control bit 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid int0 pin one-shot trigger active edge selection bit 0 : falling edge trigger 1 : rising edge trigger @ @@@@ b7 b0 one-shot start register (ons : address 002a 16 ) timer z one-shot start bit 0 : one-shot stop 1 : one-shot start not used (return ??when read)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 25 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 25 block diagram of timer 1 and timer a timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus p0 0 /cntr 1 cntr 1 active edge switch bit f(x in )/16 rising edge detected falling edge detected timer a operation mode bit timer a count stop bit prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) f(x in )/16 data bus timer a interrupt request bit timer 1 interrupt request bit pulse width hl continuously measurement mode period measurement mode
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 26 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 26 block diagram of timer x, timer y and timer z q q t toggle flip-flop timer y count stop bit programmable waveform gengeration mode f(x in )/16 f(x in )/2 timer y count source selection bits waveform extension function timer y primary waveform extension control bit p0 1 /ty out timer y output level latch q q t f(x in )/16 waveform extension function timer z primary waveform extenstion control bit p0 2 /tz out int 0 interrupt request bit p3 7 /int 0 f(x in )/2 timer z count stop bit ring oscillator clock ring (ring oscillator output in fig. 47, 48) q q p1 4 /cntr 0 r t f(x in )/16 f(x in )/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits f(x in ) p0 3 /tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus ? ? ? ? writing to timer x latch pulse output mode p0 3 /tx out output valid port p0 3 latch port p0 3 direction register prescaler y latch (8) prescaler y (8) timer y primary latch (8) timer y (8) data bus timer y secondary latch (8) timer y interrupt request bit port p0 1 latch port p0 1 direction register timer y secondary waveform extension control bit prescaler z latch (8) prescaler z (8) timer z primary latch (8) timer z (8) data bus timer z secondary latch (8) timer z interrupt request bit timer z count source selection bits one-shot pulse trigger input int 0 pin trigger active edge selection bit programmable one-shot generation mode programmable wait one-shot generation mode timer z one-shot start bit timer z secondary waveform extenstion control bit port p0 2 latch port p0 2 direction register toggle flip flop timer z output level latch programmable waveform generation mode programmable one-shot generation mode
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 27 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 27 block diagram of clock synchronous serial i/o1 fig. 28 operation of clock synchronous serial i/o1 function serial i/o l serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6) to 1. for clock synchronous serial i/o 1, the transmitter and the re- ceiver must use the same clock. if an internal clock is used, trans- fer is started by a write signal to the tb/rb. 1/4 1/4 f/f p1 2 /s clk1 serial i/o1 status register serial i/o1 control register p1 3 /s rdy1 p1 0 /r x d 1 p1 1 /t x d 1 x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy1
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 28 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 29 block diagram of uart serial i/o1 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be trans- mitted, and the receive buffer register can hold a character while the next character is being received. x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p1 2 /s clk1 serial i/o1 status register p1 0 /r x d 1 p1 1 /t x d 1
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 29 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 30 operation of uart serial i/o1 function tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ] ] serial output t x d serial input r x d receive buffer read signal [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is trans- ferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, includ- ing the error flags. all bits of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the p1 1 /txd 1 , p1 2 /s clk1 pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 30 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 31 structure of serial i/o1-related registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ??when read) serial i/o1 status register serial i/o1 control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p1 3 pin operates as ordinary i/o pin 1: p1 3 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p1 0 to p1 3 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p1 0 to p1 3 operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p1 1 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ??when read) b0 (sio1sts : address 0019 16 ) (sio1con : address 001a 16 ) (uartcon : address 001b 16 )
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 31 preliminary notice: this is not a final specification. some parametric limits are subject to change. l serial i/o2 the serial i/o2 function can be used only for clock synchronous se- rial i/o. for clock synchronous serial i/o2 the transmitter and the receiver must use the same clock. when the internal clock is used, transfer is started by a write signal to the serial i/o2 register. note: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. [serial i/o2 control register] sio2con the serial i/o2 control register contains 8 bits which control various serial i/o functions. ? set 0 to bit 3 to receive. ? at reception, clear bit 7 to 0 by writing a dummy data to the serial i/o2 register after completion of shift. fig. 32 structure of serial i/o2 control registers fig. 33 block diagram of serial i/o2 internal synchronous clock selection bits 000 : f(x in )/8 001 : f(x in )/16 010 : f(x in )/32 011 : f(x in )/64 110 : f(x in )/128 111 : f(x in )/256 b7 b0 not used (returns ??when read) transfer direction selection bit 0 : lsb first 1 : msb first s clk2 pin selection bit 0 : external clock (s clk2 is an input) 1 : internal clock (s clk2 is an output) transmit / receive shift completion flag 0 : shift in progress 1 : shift completed note : when using it as a s data input, set the port p1 3 direction register to ?? serial i/o2 control register (sio2con: address 0030 16 ) s data2 pin selection bit (note) 0 : i/o port / s data2 input 1 : s data2 output ? ? ? ? ? ? 1/8 1/16 1/32 1/64 1/128 1/256 x in data bus serial i/o2 interrupt request s data2 pin selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) s clk2 pin selection bit internal synchronous clock selection bits divider p1 2 /s clk2 p1 3 /s data2 p1 2 latch s clk2 pin selection bit s clk p1 3 latch s data2 pin selection bit
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 32 preliminary notice: this is not a final specification. some parametric limits are subject to change. serial i/o2 operation by writing to the serial i/o2 register (address 0031 16 ) the serial i/o2 counter is set to 7. after writing, the s data2 pin outputs data every time the transfer clock shifts from h to l. and, as the transfer clock shifts from l to h, the s data2 pin reads data, and at the same time the contents of the serial i/o2 register are shifted by 1 bit. when the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. ? serial i/o2 counter is cleared to 0. ? transfer clock stops at an h level. ? interrupt request bit is set. ? shift completion flag is set. also, the s data2 pin is in a high impedance state after the data transfer is completed. when the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. notice that the s data2 pin is not in a high impedance state on the comple- tion of data transfer. also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial i/o2 register. at transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial i/o2 register. fig. 34 serial i/o2 timing (lsb first) d 0 : when the internal clock is selected as the transfer, the s data2 pin is in a high impedance state after the data transfer is completed. note synchronous clock serial i/o2 register write signal transfer clock (note) s data2 at serial i/o2 input receive s data2 at serial i/o2 output transmit serial i/o2 interrupt request bit set transmit/receive shift completion flag set d 1 d 2 d 3 d 4 d 5 d 6 d 7
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 33 preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register] ad the a-d conversion register is a read-only register that stores the result of a-d conversion. do not read out this register during an a-d conversion. [a-d control register] adcon the a-d control register controls the a-d converter. bit 2 to 0 are analog input pin selection bits. bit 4 is the ad conversion completion bit. the value of this bit remains at 0 during a-d conversion, and changes to 1 at completion of a-d conversion. a-d conversion is started by setting this bit to 0. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 7 /an 7 to p2 0 /an 0, and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a-d conversion register. when a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1. because the comparator is constructed linked to a capacitor, set f(x in ) to 500 khz or more during a-d conversion. fig. 35 structure of a-d control register fig. 36 structure of a-d conversion register fig. 37 block diagram of a-d converter a-d control register (adcon : address 0034 16 ) not used (returns ??when read) not used (returns ??when read) ad conversion completion bit 0 : conversion in progress 1 : conversion completed b7 b0 analog input pin selection bits 000 : p2 0 /an 0 001 : p2 1 /an 1 010 : p2 2 /an 2 011 : p2 3 /an 3 100 : p2 4 /an 4 101 : p2 5 /an 5 110 : p2 6 /an 6 (note) 111 : p2 7 /an 7 (note) note: these can be used only for 36 pin version. read 8-bit (read only address 0035 16 ) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 (address 0035 16 ) read 10-bit (read in order address 0036 16 , 0035 16 ) b7 b0 b9 b8 (address 0036 16 ) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 (address 0035 16 ) note: high-order 6-bit of address 0036 16 returns ??when read. a-d control register (address 0034 16 ) channel selector a-d control circuit resistor ladder v ref comparator a-d interrupt request b7 b0 data bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 p2 6 /an 6 p2 7 /an 7 a-d conversion register (low-order) (address 0036 16 ) (address 0035 16 ) a-d conversion register (high-order) v ss
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 34 preliminary notice: this is not a final specification. some parametric limits are subject to change. watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8- bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control register (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accordingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp in- struction disable bit and watchdog timer h count source selection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer h is set to ff 16 and the watchdog timer l is set to ff 16 . operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is 0, the count source becomes a watchdog timer l underflow signal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is 1, the count source becomes f(x in )/16. in this case, the detection time is 512 s at f(x in )=8 mhz. this bit is cleared to 0 after reset. operation of stp instruction disable bit when the watchdog timer is in operation, the stp instruction can be disabled by bit 6 of the watchdog timer control register (address 0039 16 ). when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled, and an internal reset occurs if the stp instruction is executed. once this bit is set to 1, it cannot be changed to 0 by program. this bit is cleared to 0 after reset. fig. 38 block diagram of watchdog timer fig. 39 structure of watchdog timer control register x in data bus ? ? 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) write "ff 16 " to the watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ?f 16 ?to the watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 b7 b0
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 35 preliminary notice: this is not a final specification. some parametric limits are subject to change. reset circuit ______ the microcomputer is put into a reset status by holding the reset pin at the l level for 2 s or more when the power source voltage is 2.2 to 5.5 v and x in is in stable oscillation. ______ after that, this reset status is released by returning the reset pin to the h level. the program starts from the address having the con- tents of address fffd 16 as high-order address and the contents of address fffc 16 as low-order address. in the case of f( f ) 4 mhz, the reset input voltage must be 0.8 v or less when the power source voltage passes 4.0 v. in the case of f( f ) 2 mhz, the reset input voltage must be 0.48 v or less when the power source voltage passes 2.4 v. in the case of f( f ) 1 mhz, the reset input voltage must be 0.44 v or less when the power source voltage passes 2.2 v. fig. 40 example of reset circuit fig. 41 timing diagram at reset (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc = 2.2 v data address 8-13 clock cycles reset address from the vector table 1 : a built-in ring oscillator applies about ring? mhz, f ?50 khz frequency clock at average of vcc = 5 v. 2 : the mark ??means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes f reset reset out sync ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ?? ? clock from built-in ring oscillator ring
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 36 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 42 internal status of microcomputer at reset prescaler 1 timer 1 one-shot start register timer x mode register prescaler x timer x timer count source set register serial i/o2 control register a-d control register misrg watchdog timer control register interrupt edge selection register cpu mode register interrupt request register 1 interrupt control register 1 processor status register program counter (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) contents of address fffc 16 (pc h ) (pc l ) ff 16 01 16 00 16 00 16 ff 16 ff 16 00 16 00 16 10 16 00 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 0030 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003e 16 (ps) note x : undefined contents of address fffd 16 0011 1111 00 16 00 16 00 16 1000 0000 xxxx x1xx port p0 direction register port p1 direction register port p2 direction register port p3 direction register pull-up control register (1) (2) (3) (4) (5) register contents 00 16 00 16 00 16 00 16 0001 16 0003 16 0005 16 0007 16 0016 16 serial i/o1 control register uart control register (8) (9) serial i/o1 status register (7) 001a 16 001b 16 02 16 1110 0000 0019 16 1000 0001 xx x 0 0000 address port p1p3 control register (6) 0017 16 00 16 timer a mode register timer a (low-order) timer a (high-order) 00 16 ff 16 ff 16 001d 16 001e 16 001f 16 timer y, z mode register prescaler y timer y secondary 00 16 ff 16 ff 16 0020 16 0021 16 0022 16 timer y primary timer y, z waveform output control register prescaler z ff 16 00 16 ff 16 0023 16 0024 16 0025 16 timer z secondary ff 16 0026 16 timer z primary ff 16 0027 16 (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) serial i/o2 register 00 16 0031 16 interrupt request register 2 003d 16 00 16 interrupt control register 2 003f 16 00 16 (37) (38) (39) (40)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 37 preliminary notice: this is not a final specification. some parametric limits are subject to change. clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. set the constants of the resistor and capacitor when an rc oscillator is used, so that a frequency variation due to lsi variation and resis- tor and capacitor variations may not exceed the standard input fre- quency. l oscillation control ? stop mode when the stp instruction is executed, the internal clock f stops at an h level and the x in oscillator stops. at this time, timer 1 is set to 01 16 and prescaler 1 is set to ff 16 when the oscillation stabi- lization time set bit after release of the stp instruction is 0. on the other hand, timer 1 and prescaler 1 are not set when the above bit is 1. accordingly, set the wait time fit for the oscillation stabiliza- tion time of the oscillator to be used. f(x in )/16 is forcibly connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock f remains at h until timer 1 underflows. as soon as timer 1 underflows, the internal clock f is supplied. this is because when a ceramic oscillator is used, some time is required until a start of oscillation. in case oscil- lation is restarted by reset, no wait time is generated. so apply an l level to the reset pin while oscillation becomes stable. also, the stp instruction cannot be used while cpu is operating by a ring oscillator. ? wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator does not stop. the internal clock restarts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. when the stp status is released, prescaler 1 and timer 1 will start counting clock which is x in divided by 16, so set the timer 1 inter- rupt enable bit to 0 before the stp instruction is executed. note for use with the oscillation stabilization set bit after release of the stp instruction set to 1, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. l switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is selected by setting bit 5 of the cpu mode register. l double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. l cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. (the emulator mcu m37540rss is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. l clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 49 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 49.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 38 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 43 external circuit of ceramic resonator fig. 44 external circuit of rc oscillation fig. 46 structure of misrg fig. 45 external clock input circuit x in c out c in x out x in x out c r x in x out external oscillation circuit v cc v ss open misrg(address 0038 16 ) b7 b0 oscillation stabilization time set bit after release of the stp instruction 0: set ?1 16 ?in timer1, and ?f 16 in prescaler 1 automatically 1: not set automatically reserved bits (return ??when read) (do not write ??to these bits) not used (return ??when read)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 39 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 47 block diagram of internal clock generating circuit (for ceramic resonator) fig. 48 block diagram of internal clock generating circuit (for rc oscillation) s r q s r q 1/2 rd r s q rf 1/4 1/2 wit instruction stp instruction timing f (internal clock) stp instruction interrupt request reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 main clock division ratio selection bit double-speed mode ring oscillator mode ring oscillator (note) note : ring oscillator is used only for starting. x out x in 1/8 s r q s r q 1/2 r s q 1/4 1/2 wit instruction stp instruction timing f (internal clock) stp instruction interrupt request reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 main clock division ratio selection bit double-speed mode ring oscillator mode ring oscillator (note) note: ring oscillator is used only for starting. x out x in delay 1/8
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 40 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 49 state transition state 1 operation clock source: x in x in oscillation enabled ring oscillator stop cm3 0 2 cm7,6 10 2 cm4 1 2 cm4 0 2 cm7,6 not(10 2 ) cm3 1 2 cm4 1 2 cm4 1 2 cm3 1 2 cm3 1 2 cm7,6 not(10 2 ) cm4 0 2 cm7,6 not(10 2 ) cm4 0 2 cm3 1 2 cm7,6 10 2 cm3 0 2 cm7,6 10 2 2 cm3 0 2 cm7,6 10 2 cm4 1 2 cm7,6 not(10 2 ) cm3 1 2 state 2 operation clock source: x in x in oscillation enabled ring oscillator enalbed state 3 (initial state after reset) operation clock source: ring oscillator x in oscillation enabled ring oscillator enalbed state 4 (low power dissipation mode operation clock source: ring oscillator x in oscillation stop ring oscillator enalbed by ring oscillator) cm4 1 notes on switch of clock (1) execute the state transition from state 3 to state 2 after stabilizing x in oscillation. (2) do not execute the state transition shown (3) in operation clock source = x in , the double-speed mode, high-speed mode, and middle-speed mode can be selected for the cpu clock division ratio. (4) in operation clock source = ring oscillator, the middle-speed mode is selected for the cpu clock division ratio. (5) do not stop the clock selected as the operation clock because of setting of cm3, 4. .
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 41 preliminary notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is 1. after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the pre- vious contents. for executing the instruction for the changed con- tents, execute one instruction before executing the bbc or bbs in- struction. decimal calculations ? for calculations in decimal notation, set the decimal mode flag d to 1, then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld instruction after executing one instruction before the adc instruction or sbc instruction. ? in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. timers ? when n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ? when a count source of timer x, timer y or timer z is switched, stop a count of timer x. ports ? the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is 1, addressing mode using di- rection register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. ? p2 6 /an 6 , p2 7 /an 7 , p3 5 (led 5 ), p3 6 /int 1 pins do not exist in the 32-pin version. stabilize the internal level by setting the port direc- tion registers of these ports to output or setting p3 5 , p3 6 pull-up control bits of the pull-up control register (pull) to on by pro- gram. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is 500khz or more during a-d conversion. do not execute the stp instruction during a-d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock f by the number of cycles mentioned in the machine-language instruction table. the frequency of the internal clock f is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is excluded.) when a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. state transition do not stop the clock selected as the operation clock because of setting of cm3, 4. notes on use handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be lo- cated too far from the pins to be connected, a ceramic capacitor of 0.01 f to 0.1 f is recommended. one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin with 1 to 10 k w resistance. the mask rom version track of cnvss pin has no operational inter- ference even if it is connected via a resistor.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 42 preliminary notice: this is not a final specification. some parametric limits are subject to change. data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version can be read or programmed with a general-purpose prom programmer us- ing a special programming adapter. set the address of prom pro- grammer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 50 is recommended to verify programming. package 32p4b 32p6b-a 36p2r-a name of programming adapter pca7435spg02 pca7435gpg02 pca7435fpg02 table 5 special programming adapter fig. 50 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution:
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 43 preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics 1.7540group (general purpose) applied to: m37540m4-xxxfp/sp/gp, m37540e8fp/sp/gp absolute maximum ratings (general purpose) table 6 absolute maximum ratings C0.3 to 7.0 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 C0.3 to v cc + 0.3 300 (note 2) C20 to 85 C40 to 125 power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 , v ref input voltage reset, x in input voltage cnv ss (note 1) output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 , x out power dissipation operating temperature storage temperature v v v v v mw c c v cc v i v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25c note 1: it is a rating only for the one time prom version. connect to v ss for the mask rom version. 2: 200 mw for the 32p6b package product.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 44 preliminary notice: this is not a final specification. some parametric limits are subject to change. recommended operating conditions (general purpose) table 7 recommended operating conditions (1) (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc 4.0 2.4 2.2 4.0 2.4 2.2 4.0 2.4 2.2 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (double- speed mode ) f(x in ) = 2 mhz (double- speed mode ) f(x in ) = 1 mhz (double- speed mode ) f(x in ) = 4 mhz ( high-, middle-speed mode ) f(x in ) = 2 mhz ( high-, middle-speed mode ) f(x in ) = 1 mhz ( high-, middle-speed mode ) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v power source voltage analog reference voltage h input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l total peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l total peak output current (note 2) p3 0 Cp3 6 h total average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l total average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l total average output current (note 2) p3 0 Cp3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. v cc v cc 0.3v cc 0.8 0.2v cc 0.16v cc C80 80 60 C40 40 30 v ss v ref v ih v ih v ih v il v il v il v il ? i oh(peak) ? i ol(peak) ? i ol(peak) ? i oh(avg) ? i ol(avg) ? i ol(avg) power source voltage (rc) v v v v v v ma ma ma ma ma ma
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 45 preliminary notice: this is not a final specification. some parametric limits are subject to change. recommended operating conditions (general purpose)(continued) table 8 recommended operating conditions (2) (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) h peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l peak output current (note 1) p3 0 Cp3 6 h average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l average output current (note 2) p3 0 Cp3 6 internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. C10 10 30 C5 5 15 4 2 1 8 4 2 4 2 1 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in )
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 46 preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics (general purpose) table 9 electrical characteristics (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = C5 ma v cc = 4.0 to 5.5 v i oh = C1.0 ma v cc = 2.2 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.2 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.2 to 5.5 v v i = v cc (pin floating. pull up transistors off) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off) v i = v ss v i = v ss v i = v ss (pull up transistors on) test conditions v cc C1.5 v cc C1.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l output voltage p3 0 Cp3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 Cp0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis h input current p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l input current reset, cnv ss l input current x in l input current p0 0 Cp0 7 , p3 0 Cp3 7 ram hold voltage 1.5 0.3 1.0 2.0 0.3 v v v v v v v v oh v ol v ol 0.4 v v t+ Cv tC v 0.5 0.5 4.0 C4.0 C0.2 5.0 5.0 C5.0 C5.0 C0.5 5.5 v a a a a a a ma v v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il i il v ram when clock stopped 2.0 reset 1.0 v i cc power source current 5.0 ta = 25 c ta = 85 c tbd 5.0 2.0 0.1 1.6 tbd 0.7 tbd tbd tbd tbd 1.0 10 ma ma ma ma ma ma ma a a high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors off double-speed mode, f(x in ) = 4 mhz output transistors off middle-speed mode, f(x in ) = 8 mhz output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.2 v (in wit state) output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: r x d1, s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 47 preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter characteristics (general purpose) table 10 a-d converter characteristics (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) v cc = v ref = 5.12 v v cc = v ref = 3.072 v resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 c v cc = 2.7 to 5.5 v ta = 25 c v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v 0 0 5105 3060 50 30 5 3 5115 3069 20 15 5125 3075 122 200 35 150 mv mv mv mv tc(x in ) k w lsb lsb bits 0.9 3 10 v ot v fst t conv r ladder i vref i i(ad) a 5.0 a v ref = 3.0 v 120 90
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 48 preliminary notice: this is not a final specification. some parametric limits are subject to change. timing requirements (general purpose) table 11 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 Cs clk1 ) t h (rxd 1 Cs clk1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 Cs clk2 ) t h (s clk2 Cs data2 ) 2 125 50 50 200 80 80 200 80 80 2000 950 950 400 200 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 49 preliminary notice: this is not a final specification. some parametric limits are subject to change. table 12 timing requirements (2) (v cc = 2.2 to 5.5 v or 2.4 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. symbol parameter unit min. typ. limits t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (s data1 Cs clk1 ) t h (s clk1 Cs data1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 Cs clk2 ) t h (s clk2 Cs data2 ) reset input l pulse width external clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v external clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v external clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 , int 0 , int 1 , input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 , int 0 , int 1 , input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 input set up time serial i/o2 input hold time 2 500 250 200 100 200 100 1000 500 460 230 460 230 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 4000 2000 1900 950 1900 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 50 preliminary notice: this is not a final specification. some parametric limits are subject to change. switching characteristics (general purpose) table 13 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C30 t c (s clk2 )/2C30 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ctxd 1 ) t v (s clk1 Ctxd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs data2 ) t v (s clk2 Cs data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 14 switching characteristics (2) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit tbd tbd tbd 350 50 50 50 50 note 1: pin x out is excluded. switching characteristics measurement circuit diagram (gen- eral purpose) / / / measured output pin cmos output 100 pf t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ct x d 1 ) t v (s clk1 Ct x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs data2 ) t v (s clk2 Cs data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) tbd tbd tbd t c (s clk2 )/2C50 t c (s clk2 )/2C50 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 51 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 51 timing chart (general purpose) 0.2v cc t d (s clk1 -s data1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data1 -s clk1 )t h (s clk1 -s data1 ) t v (s clk1 -s data1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 52 preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics 2.7540group (extended operating temperature version) applied to: M37540M4T-XXXFP/gp absolute maximum ratings (extended operating temperature version) table 15 absolute maximum ratings C0.3 to 7.0 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 300 (note) C40 to 85 C65 to 150 power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 , v ref input voltage reset, x in , cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 , x out power dissipation operating temperature storage temperature v v v v mw c c v cc v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25c note : 200 mw for the 32p6b package product.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 53 preliminary notice: this is not a final specification. some parametric limits are subject to change. recommended operating conditions (extended operating temperature version) table 16 recommended operating conditions (1) (v cc = 2.2 to 5.5 v, ta = C40 to 85 c, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 0.3v cc 0.8 0.2v cc 0.16v cc C80 80 60 C40 40 30 4.0 2.4 2.2 4.0 2.4 4.0 2.4 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (double- speed mode ) f(x in ) = 2 mhz (double- speed mode ) f(x in ) = 4 mhz ( high-, middle-speed mode ) f(x in ) = 2 mhz ( high-, middle-speed mode ) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage h input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l total peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l total peak output current (note 2) p3 0 Cp3 6 h total average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l total average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l total average output current (note 2) p3 0 Cp3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. v ss v ref v ih v ih v ih v il v il v il v il a i oh(peak) a i ol(peak) a i ol(peak) a i oh(avg) a i ol(avg) a i ol(avg) power source voltage (rc)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 54 preliminary notice: this is not a final specification. some parametric limits are subject to change. recommended operating conditions (extended operating temperature version) table 17 recommended operating conditions (2) (v cc = 2.2 to 5.5 v, ta = C40 to 85 c, unless otherwise noted) h peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l peak output current (note 1) p3 0 Cp3 6 h average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l average output current (note 2) p3 0 Cp3 6 internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. C10 10 30 C5 5 15 4 2 8 4 2 4 2 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in )
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 55 preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics (extended operating temperature version) table 18 electrical characteristics (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = C5 ma v cc = 4.0 to 5.5 v i oh = C1.0 ma v cc = 2.2 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.2 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.2 to 5.5 v v i = v cc (pin floating. pull up transistors off) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off) v i = v ss v i = v ss v i = v ss (pull up transistors on) test conditions v cc C1.5 v cc C1.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 7 l output voltage p3 0 Cp3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 Cp0 7 (note 3) hysteresis r x d 1 , s clk1 , s clk2 , s data2 (note 2) hysteresis h input current p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 4 , p2 0 Cp2 7 , p3 0 Cp3 7 l input current reset, cnv ss l input current x in l input current p0 0 Cp0 7 , p3 0 Cp3 7 ram hold voltage 1.5 0.3 1.0 2.0 0.3 v v v v v v v v oh v ol v ol 0.4 v v t+ Cv tC v 0.5 0.5 4.0 C4.0 C0.2 5.0 5.0 C5.0 C5.0 C0.5 5.5 v a a a a a a ma v v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il i il v ram when clock stopped 2.0 reset 1.0 v i cc power source current 5.0 ta = 25 c ta = 85 c tbd 5.0 2.0 0.1 1.6 tbd 0.7 tbd tbd tbd tbd 1.0 10 ma ma ma ma ma ma ma a a high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors off double-speed mode, f(x in ) = 4 mhz output transistors off middle-speed mode, f(x in ) = 8 mhz output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.2 v (in wit state) output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: r x d 1 , s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 56 preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter characteristics (extended operating temperature version) table 19 a-d converter characteristics (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) v cc = v ref = 5.12 v v cc = v ref = 3.072 v resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 c v cc = 2.7 to 5.5 v ta = 25 c v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v 0 0 5105 3060 50 30 5 3 5115 3069 20 15 5125 3075 122 200 35 150 mv mv mv mv tc(x in ) k w lsb lsb bits 0.9 3 10 v ot v fst t conv r ladder i vref i i(ad) a 5.0 a v ref = 3.0 v 120 90
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 57 preliminary notice: this is not a final specification. some parametric limits are subject to change. timing requirements (extended operating temperature version) table 20 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 Cs clk1 ) t h (rxd 1 Cs clk1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 Cs clk2 ) t h (s clk2 Cs data2 ) 2 125 50 50 200 80 80 200 80 80 2000 950 950 400 200 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 58 preliminary notice: this is not a final specification. some parametric limits are subject to change. table 21 timing requirements (2) (v cc = 2.2 to 5.5 v or 2.4 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) max. symbol parameter unit min. typ. limits t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (s data1 Cs clk1 ) t h (s clk1 Cs data1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 Cs clk2 ) t h (s clk2 Cs data2 ) reset input l pulse width external clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v external clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v external clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 , int 0 , int 1 , input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 0 , int 0 , int 1 , input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v cntr 1 input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 clock input h pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 clock input l pulse width v cc = 2.2 to 5.5 v v cc = 2.4 to 5.5 v serial i/o2 input set up time serial i/o2 input hold time 2 500 250 200 100 200 100 1000 500 460 230 460 230 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 4000 2000 1900 950 1900 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 59 preliminary notice: this is not a final specification. some parametric limits are subject to change. switching characteristics (extended operating temperature version) table 22 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C30 t c (s clk2 )/2C30 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ctxd 1 ) t v (s clk1 Ctxd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs data2 ) t v (s clk2 Cs data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 23 switching characteristics (2) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit tbd tbd tbd 350 50 50 50 50 note 1: pin x out is excluded. switching characteristics measurement circuit diagram (gen- eral purpose) / / / measured output pin cmos output 100 pf t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ct x d 1 ) t v (s clk1 Ct x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs data2 ) t v (s clk2 Cs data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) tbd tbd tbd t c (s clk2 )/2C50 t c (s clk2 )/2C50 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 60 preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 52 timing chart (extended operating temperature version) 0.2v cc t d (s clk1 -s data1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data1 -s clk1 )t h (s clk1 -s data1 ) t v (s clk1 -s data1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit)
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 61 preliminary notice: this is not a final specification. some parametric limits are subject to change. package outline lqfp32-p-77-0.80 weight(g) 0.17 jedec code eiaj package code lead material alloy 42 32p6b-a plastic 32pin 7 5 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.5 i 2 1.0 m d 7.4 m e 7.4 10 0 0.1 1.0 0.7 0.5 0.3 9.2 9.0 8.8 9.2 9.0 8.8 0.8 7.1 7.0 6.9 7.1 7.0 6.9 0.175 0.125 0.105 0.45 0.35 0.3 1.4 0 1.7 e a 1 a 2 l 1 l detail f lp a3 c e e h e 1 8 9 32 25 24 16 17 h d d m d m e a f y b 2 i 2 recommended mount pad b x m lp 0.45 0.6 0.25 0.75 0.2 x a3 e ssop36-p-450-0.80 weight(g) jedec code 0.53 eiaj package code lead material alloy 42 36p2r-a plastic 36pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .35 0 .05 0 .13 0 .8 14 .2 8 .63 11 .3 0 .27 1 .0 2 .4 0 .15 0 .0 15 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .5 0 .2 0 .2 15 .6 8 .23 12 .7 0 .15 0 b 2 ?5 0 0 ?0 e e 1 36 19 18 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g z 1 0.7 0.85 z b g
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 62 preliminary notice: this is not a final specification. some parametric limits are subject to change. sdip32-p-400-1.78 weight(g) 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 1.778 10.16 3.0 0 ?5 5.08 e e 1 32 17 16 1 e c e 1 a 2 a 1 b 2 b b 1 e la seating plane d
? 1999 mitsubishi electric corp. new publication, effective nov. 1999. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers
rev. rev. no. date 1.0 first edition 991122 revision history 7540 group data sheet (1/1) revision description

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